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Senior Digital Design Engineer Power Management

Job Code:  2549
Location: CHANDLER, AZ US
Travel Involved: None
Job Type: Full Time
Job Level:  See posting requirements below
Education: Master's Degree 
Skills:  
Category: Semiconductor
Position Summary:

Join a team of worldwide leaders in the design, development and manufacturing of analog, mixed signal, high frequency and digital integrated circuits. Maxim is growing in the area of digital and mixed-signal design.  As we continue our migration to smaller geometry process nodes, we anticipate increasing digital and mixed-signal content.  Help us expand and complement our strong analog and power management design teams. 


Maxim is looking for a senior Digital/Mixed-Signal Design Engineer possessing digital power conversion controller development experience to join a team working on leading edge technology development.  The preferred candidate would have successfully brought to market  products with high performance embedded digital controllers.  Additional experience in high speed asynchronous custom logic, mixed signal simulation, Verilog and VHDL modeling, and design verification is also preferred.
Responsibilities will include the full range of design tasks from initial concept, through architecture and implementation, to final realization and productization.   This is a unique opportunity to chart a new course in power conversion, in collaboration with a strong team of senior analog, digital, mixed-signal, and verification engineers, to create and deliver a successful new product family. 
The candidate must want to contribute in a team environment.

Requirements:

- MSEE  degree with 8+ years experience in Digital and/or Mixed-Signal Design
- at least 5 years in RTL/Synthesis based ASIC Design
- at least 2 years in designing digital circuits which interface analog circuits such as linear regulators, buck converters, and data converters.
- Verilog/VHDL language & simulation verification experience
- Mixed-signal simulation (Cadence AMS), interfacing with analog functions
- Logic Synthesis, Static Timing Analysis, and Logic Equivalency Checking.
- Design for test, scan insertion, ATPG, Functional Test Vectors
- Interfacing with Place & Route Engineer, Back-annotated simulation verification
- Taken at least 5 projects through entire flow from specification to production
- The individual must have the knowledge and capability to execute the entire design process without significant assistance
- FPGA experience is a plus but not mandatory.
- Universal Verification Methodology (UVM) experience is a plus but not mandatory.


Maxim is an EEO/AA Employer

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